Siliscale’s BlogASIC RTL design, FPGA RTL design, ASIC and FPGA RTL verification. Embedded Linux: kernel drivers, BSPs, Yocto/Buildroot.https://siliscale.comReducing Dynamic Power in Booth-Encoded Multipliers Through Zero Representation Selectionhttps://siliscale.com/booth-power-reductionhttps://siliscale.com/booth-power-reductionA “free” power optimization in Modified Booth encoding by choosing +0 instead of −0 in one’s complement partial products.Thu, 01 Jan 2026 00:00:00 GMTRegister Scoreboards: Beyond Simple Forwarding in Pipelined Processorshttps://siliscale.com/register-scoreboardhttps://siliscale.com/register-scoreboardWhy operand forwarding alone breaks down with multi-cycle operations—and how a register scoreboard fixes it.Sat, 27 Dec 2025 00:00:00 GMTMastering External Signal Synchronization in FPGA Designhttps://siliscale.com/ext-sig-synchttps://siliscale.com/ext-sig-syncIn the world of FPGA design, few challenges are as fundamental yet critical as handling external asynchronous signals.Fri, 27 Jun 2025 00:00:00 GMTHow to compile a Large Language Model (LLM) to RISC-Vhttps://siliscale.com/llm-to-riscvhttps://siliscale.com/llm-to-riscvIn this article, we will explore how to compile a Large-Language Model like Bert and generate RISC-V vector extension codeMon, 04 Nov 2024 00:00:00 GMTHow to generate RISC-V vector code from Tensorflowhttps://siliscale.com/riscv-from-tfhttps://siliscale.com/riscv-from-tfIn this article, we will explore how to generate RISC-V vector extension assembly from Tensorflow via XLA.Mon, 04 Nov 2024 00:00:00 GMTXilinx QDMA IP Core Tutorialhttps://siliscale.com/xilinx-qdma-tutorialhttps://siliscale.com/xilinx-qdma-tutorialIn this article, we will explore how to use the Xilinx QDMA IP core to create a PCIe device and access it over Linux.Sat, 04 Nov 2023 00:00:00 GMT