· FPGA
Mastering External Signal Synchronization in FPGA Design
In the world of FPGA design, few challenges are as fundamental yet critical as handling external asynchronous signals.
Blog
A collection of articles and tutorials.
How to compile a Large Language Model (LLM) to RISC-V
In this article, we will explore how to compile a Large-Language Model like Bert and generate RISC-V vector extension code
How to generate RISC-V vector code from Tensorflow
In this article, we will explore how to generate RISC-V vector extension assembly from Tensorflow via XLA.
- · FPGA
Xilinx QDMA IP Core Tutorial
In this article, we will explore how to use the Xilinx QDMA IP core to create a PCIe device and access it over Linux.
