About Siliscale
Siliscale — ASIC and FPGA RTL design and verification, licensed FPGA IP cores, and embedded systems programming. Presence in the US, Mainland Europe, and the Canary Islands.
Who we are
We write and verify RTL (SystemVerilog/Verilog/VHDL) for ASIC and FPGA programs, and we write the Linux stack that talks to those registers — kernel drivers, BSPs, Yocto/Buildroot.
The same work is in the open: Tiny-Vedas is our RISC-V AI accelerator stack, from the core and GEMM datapath through a PyTorch compiler. Licensed IP is separate: Nadi DMA is a 33 ns PCIe DMA core for UltraScale+.
Where we work from
Registered headquarters: Cheyenne, Wyoming. Engineering across time zones for customer chip and software teams.
European office for collaboration with EU customers and vendors.
R&D and operations base supporting remote delivery.
What we do
Synthesizable RTL for silicon — microarchitecture, SoC/IP integration, LINT/CDC/RDC, STA/DFT handoff.
Fabric-aware RTL — vendor IP, CDC/clocking, Vivado/Quartus constraints, timing closure.
ASIC RTL verification (UVM/tapeout) and FPGA RTL verification (CDC/integration/lab).
Linux kernel drivers, DMA/IRQ, device tree, BSP, Yocto/Buildroot.
Licensed encrypted IP. Nadi DMA is a 33 ns PCIe DMA engine for UltraScale+.
How we engage
We follow your coding standards, CI, and review process. Reviewable diffs your team keeps.
RTL and UVM that match the MMIO map; drivers and BSPs written against that hardware.
Linux, Yocto/Buildroot, and upstream patches when that is the right delivery path.
Clear block or DV ownership, milestones, and handoff — not theater.
Need RTL, UVM, or drivers?
Tell us the block, interfaces, and toolchain. We’ll say what we’d own in the first two weeks.
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