Packet processing and data capture at 100G+
Line-rate FPGA datapaths that parse, filter, timestamp and move every packet or sample to the host without drops.
The problem
At 100G, a minimum-size packet arrives every 6.7 ns. Software can't keep up, and a capture with gaps is worthless. The hard parts are sustaining line rate indefinitely, stamping every packet precisely, and getting the data to the host without the CPU in the way.
What we build
- Packet parsing and filtering at line rate
- Hardware timestamping
- Lossless capture with buffering and back-pressure
- PCIe DMA to host memory
- 10/25/100G Ethernet MAC integration
- Host drivers and capture software
Proof
Markets
- Network monitoring and packet brokers
- Security and intrusion detection
- Lawful interception and SIGINT
- Finance (tick capture)
- Test & measurement analyzers
- Chip test (ATE) capture
How we work
Full-time equivalent
An embedded engineering capacity billed monthly, for open-ended R&D and ongoing development.
Project
A fixed scope at a fixed price, for work we've done before.
Hybrid
A paid scoping phase that produces the spec, then a fixed-price build.
Discuss your project
Share the target, interfaces, and timeline. We’ll tell you what we’d take on first.