SoC design services
We design SoCs and ASIC blocks to your spec, from the architecture to RTL ready for synthesis, and prove them on FPGA before tapeout.
What we design
- SoC architecture and microarchitecture
- Processor subsystems: RISC-V, Arm or your own cores
- Interconnect, caches, DMA and memory controllers
- Accelerators and custom datapaths
- Clock, reset and power domains
- Third-party IP integration
- Full-SoC prototypes on FPGA
- Synthesis-ready RTL and handoff to physical design
How we work
- 01 Spec and architecture, with the performance targets written down before any RTL.
- 02 RTL in SystemVerilog, lint and CDC clean, structured for synthesis and timing.
- 03 Verification alongside the design, not after it.
- 04 An FPGA prototype that runs your software before tapeout.
- 05 Handoff to your physical design team or partner, with constraints and documentation.
Frequently asked questions
Is this ASIC design?
Yes. We write SoC and ASIC RTL for silicon: synthesis-ready, with constraints, and prototyped on FPGA first so the software runs before tapeout.
Do we have to use your IP cores?
No. We design with whatever fits your project: your own cores, a third party’s, or ours. Our IP cores are licensed separately. See our IP cores
Can you work on an existing SoC?
Yes. We add subsystems, integrate new IP, or take over blocks inside your existing design and flow.
Do you do physical design?
We hand off to your physical design team or partner, and we design with the backend in mind. Tiny Vedas goes through the OpenROAD flow on the ASAP7 process design kit.
Discuss your project
Share the target, interfaces, and timeline. We’ll tell you what we’d take on first.