Signal processing and RF datapaths on FPGA
We build DSP chains from ADC to host: filtering, FFT and beamforming at full sample rate.
The problem
Wideband converters produce more data than any processor can take, so processing has to happen in the fabric, at full rate, with deterministic latency. Getting it right means fixed-point design that keeps precision, and a datapath that never drops samples.
What we build
- Digital down-conversion and filtering
- FFT and channelization
- Beamforming
- Triggering and acquisition
- Streaming to the host over PCIe or Ethernet
- Fixed-point modelling and bit-exact verification
Markets
- Radar and electronic warfare
- Test & measurement
- Telecom fronthaul
- Chip test (ATE)
Frequently asked questions
Do you work with direct RF sampling devices?
Yes, including AMD RFSoC devices with integrated data converters.
How do you keep fixed-point results correct?
Every block is modelled first and verified bit-exact against the model in simulation and on hardware.
Can the host receive the full sample stream?
Yes, over PCIe DMA or 100G Ethernet, sized for sustained rate.
Related
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