RTL design and verification for ASIC and FPGA
Chip design services — custom digital circuits, coverage closure, and the software that brings them up.
Services
ASIC RTL Design
Synthesizable RTL for blocks and SoCs — microarchitecture, IP integration, LINT/CDC/RDC, handoff to synthesis/STA/DFT.
FPGA RTL Design
Fabric-aware RTL — vendor IP, CDC/clocking, Vivado/Quartus constraints, timing-closure-oriented structure.
ASIC RTL Verification
UVM, functional coverage, SVA, regressions — sized for tapeout and respin risk.
FPGA RTL Verification
Integration sims, CDC/reset checks, SVA, UVM when reuse matters — aimed at bitstream and lab bring-up.
Embedded Systems Programming
Linux kernel drivers, BSPs, device tree, DMA/IRQ, Yocto/Buildroot — software against real SoC/FPGA register maps.
Research: Tiny-Vedas, open-source RISC-V infrastructure for AI accelerator design.
IP cores
Nadi DMA
PCIe DMA IP for AMD UltraScale+. 33 ns doorbell-to-completion (13 cycles at 390.625 MHz) on Alveo U280. Encrypted Vivado IP, evaluation and production licenses.
Discuss your project
Share the target, interfaces, and timeline. We’ll tell you what we’d take on first.