Line-rate cryptography on FPGA
We build encryption that runs at full network speed, including post-quantum algorithms.
The problem
Software crypto can't keep up with 100G links, and post-quantum migration deadlines are arriving for defense and government systems. Hardware has to encrypt at line rate while resisting side-channel attacks.
What we build
- AES-GCM at line rate
- MACsec and IPsec offload
- Post-quantum algorithms: ML-KEM and ML-DSA
- Hardware security module datapaths and key interfaces
- Side-channel-aware implementation
Markets
- Secure communications
- Network security appliances
- Hardware security modules
- Telecom
Frequently asked questions
Which post-quantum standards do you implement?
NIST FIPS 203 (ML-KEM) and FIPS 204 (ML-DSA).
Can it run at 100G?
That's the design target: the datapath is sized for full line rate.
How do you address side channels?
Implementations are designed for constant-time behaviour and evaluated for leakage.
Related
Discuss your project
Share the target, interfaces, and timeline. We’ll tell you what we’d take on first.